TAS5705PAP datasheet(30/71 Pages) TI

номер детали	TAS5705PAP

подробное описание детали	20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC

PDF	71 Pages

Scroll/Zoom	100%

производитель	TI [Texas Instruments]

домашняя страница	http://www.ti.com

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30 / 71 page

Right-Justified

SCLK

32Clks

LRCLK

LeftChannel

24-BitMode

20-BitMode

16-BitMode

MSB

LSB

SCLK

32Clks

RightChannel

2-ChannelRight-Justified(SonyFormat)StereoInput

T0034-03

MSB

LSB

TAS5705

SLOS549 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when

it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at

32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data line 8 bit-clock periods (for

24-bit data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before

LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks

unused leading data bit positions.

Figure 34. Right-Justified 64-fS Format

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