TAS5701PAPR datasheet(6/26 Pages) TI

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TAS5701

SLOS559 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com

TERMINAL FUNCTIONS (continued)

TERMINAL

5-V

TERMINATION

I/O(1)

DESCRIPTION

TOLERANT

(2) (3)

NAME

NO.

BST_C

High-side bootstrap supply for half-bridge C

BST_D

High-side bootstrap supply for half-bridge D

CONFIG_2

Pulldown

Input/output configuration. Connect this terminal directly to GND.

CONFIG_1

Pulldown

Input/output configuration. Connect this terminal directly to DVDD.

DVDD

15, 35

3.3-V Digital power supply

DVSS

Digital ground

DVSSO

Oscillator ground

FAULT

Overtemperature, undervoltage, and overcurrent fault reporting.

Active low indicates fault. If high, normal operation.

FORMAT2

Pulldown

Digital data format select MSB.

FORMAT1

Pulldown

Digital data format select LSB.

FORMAT0

Pulldown

Digital data format select.

GAIN_1

5-V

MSB of gain select.

GAIN_0

5-V

LSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain

selections.

GND

41, 42

Analog ground for power stage.

GVDD_AB

Gate drive voltage for half-bridges A and B (10.8 V to 13.2 V)

GVDD_CD

Gate drive voltage for half-bridges C and D (10.8 V to 13.2 V)

LRCLK

5-V

Input serial audio data left/right clock (sampling rate clock)

MCLK

5-V

Clock master input. The input frequency of this clock can range from

4.9 MHz to 49 MHz.

MUTE

5-V

Pullup

Performs a soft mute of outputs, active-low. A logic low on this pin

sets the outputs equal to 50% duty cycle. A logic high on this pin

allows normal operation. The mute control provides a noiseless

volume ramp to silence. Releasing mute provides a noiseless ramp to

previous volume.

OC_ADJ

Analog overcurrent programming. Requires 22-k

Ω resistor to ground.

OSC_RES

Oscillator trim resistor. Connect an 18.2-k

Ω (1% tolerance is

required) resistor to DVSSO.

OUT_A

1, 64

Output, half-bridge A

OUT_B

60, 61

Output, half-bridge B

OUT_C

52, 53

Output, half-bridge C

OUT_D

48, 49

Output, half-bridge D

PDN

5-V

Pullup

Power down, active-low. PDN stops all clocks, and outputs stop

switching whenever a logic low is applied. When PDN is released, the

device powers up all logic, starts all clocks, and performs a soft start

that returns to the previous configuration changes to FORMATx and

GAINx pins are ignored on PDN cycling.

PGND_AB

62, 63

Power ground for half-bridges A and B

PGND_CD

50, 51

Power ground for half-bridges C and D

PLL_FLTM

PLL negative loop filter terminal

PLL_FLTP

PLL positive loop filter terminal

PVDD_A

2, 3

Power supply input for half-bridge output A (0 V–21 V)

PVDD_B

58, 59

Power supply input for half-bridge output B (0 V–21 V)

PVDD_C

54, 55

Power supply input for half-bridge output C (0 V–21 V)

PVDD_D

46, 47

Power supply input for half-bridge output D(0 V–21 V)

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