STA015 datasheet(8/44 Pages) STMICROELECTRONICS

8 / 44 page

XTI2DSPCLK

XTI2OCLK

PFD

VCO

Switching

Circuit

OCLK

DCLK

Update FRAC

FRAC

XTI

Disable PLL

Figure 5. PLL and Clocks Generation System

2.4 - PCM Output Interface

The decoded audio data are output in serial PCM

format. The interface consists of the following sig-

nals:

SDO

PCM Serial Data Output

SCKT

PCM Serial Clock Output

LRCLK

Left/Right Channel Selection Clock

The output samples precision is selectable from

16 to 24 bits/word, by setting the output precision

with PCMCONF (16, 18, 20 and 24 bits mode)

significant bit first (MS) or least significant bit first

(LS), selected by writing into a flag of the

PCMCONF register.

Figure 8 gives a description of the several

STA015 PCM Output Formats.

The sample rates set decoded by STA015 is de-

scribed in Table 1.

LRCKT

SDO

PCM_FORMAT = 0

PCM_DIFF = 0

PCM_FORMAT = 1

PCM_DIFF = 1

32 SCLK Cycles

LRCKT

SDO

PCM_ORD = 1

PCM_PREC is 16 bit mode

PCM_ORD = 0

PCM_PREC is 16 bit mode

16 SCLK Cycles

SDO

PCM_FORMAT = 0

PCM_DIFF = 1

SDO

PCM_FORMAT = 1

PCM_DIFF = 1

MSB

Figure 6. PCM Output Formats

Table 1: MPEG Sampling Rates (KHz)

MPEG 1

MPEG 2

MPEG 2.5

44.1

22.05

11.025

STA015-STA015B-STA015T

8/44

STA015 датащи(PDF) 8 Page - STMicroelectronics

STA015 датащи(HTML) 8 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

датащи скачать

ссылки URL