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ST95P08 датащи(PDF) 12 Page - STMicroelectronics

номер детали ST95P08
подробное описание детали  8 Kbit Serial SPI EEPROM with Positive Clock Strobe
PDF  16 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST95P08 датащи(HTML) 12 Page - STMicroelectronics

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POWER ON STATE
After a Power up the ST95P08 is in the following
state:
– The device is in the low power standby state.
– The chip is deselected.
– The chip is not in hold condition.
– The write enable latch is reset.
– BP1 and BP0 are unchanged (non-volatile bits).
DATA PROTECTION AND PROTOCOL SAFETY
– All inputs are protected against noise, see Table
3.
– Non valid S and HOLD transitions are not taken
into account.
– S must come high at the proper clock count in
order to start a non-volatile write cycle (in the
memory array or in the cycle status register). The
Chip Select S must rise during the clock pulse
following the introduction of a multiple of 8 bits.
– Access to the memory array during non-volatile
programming cycle is cancelled and the chip is
automatically deselected; however, the pro-
gramming cycle continues.
– After either of the following operations (WREN,
WRDI, RDSR) is completed, the chip enters a
wait state and waits for a deselect.
– The write enable latch is reset upon power-up.
– The write enable latch is reset when W is brought
low.
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state (all data set at all "1’s" or FFh).
The block protect bits are initialized to 00.
C
D
AI01432
S
Q
2
1
3456789 10 11 12 13 14 15
HIGH IMPEDANCE
INSTRUCTION
STATUS REG.
0
Figure 13. WRSR: Write Status Register Sequence
12/16
ST95P08



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