ST90135 datasheet(158/190 Pages) STMICROELECTRONICS

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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI)

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

INTERRUPT MASK REGISTER (IMR)

R246 - Read/Write

Reset value: 0xx00000

Bit 7 = BSN:

Buffer or shift register empty inter-

rupt.

This bit selects the source of the transmitter regis-

ter empty interrupt.

0: Select a Shift Register Empty as source of a

Transmitter Register Empty interrupt.

1: Select a Buffer Register Empty as source of a

Transmitter Register Empty interrupt.

Bit 6 = RXEOB:

Received End of Block.

This bit is set by hardware only and must be reset

by software. RXEOB is set after a receiver DMA

cycle to mark the end of a data block.

0: Clear the interrupt request.

1: Mark the end of a received block of data.

Bit 5 = TXEOB:

Transmitter End of Block.

This bit is set by hardware only and must be reset

by software. TXEOB is set after a transmitter DMA

cycle to mark the end of a data block.

0: Clear the interrupt request.

1: Mark the end of a transmitted block of data.

Bit 4 = RXE:

Receiver Error Mask.

0: Disable Receiver error interrupts (OE, PE, and

FE pending bits in the S_ISR register).

1: Enable Receiver error interrupts.

Bit 3 = RXA:

Receiver Address Mask.

0: Disable Receiver Address interrupt (RXAP

pending bit in the S_ISR register).

1: Enable Receiver Address interrupt.

Bit 2 = RXB:

Receiver Break Mask.

0: Disable Receiver Break interrupt (RXBP pend-

ing bit in the S_ISR register).

1: Enable Receiver Break interrupt.

Bit 1 = RXDI:

Receiver Data Interrupt Mask.

0: Disable Receiver Data Pending and Receiver

End of Block interrupts (RXDP and RXEOB

pending bits in the S_ISR register).

1: Enable Receiver Data Pending and Receiver

End of Block interrupts.

Note: RXDI has no effect on DMA transfers.

Bit 0 = TXDI:

Transmitter Data Interrupt Mask.

0: Disable Transmitter Buffer Register Empty,

Transmitter Shift Register Empty, or Transmitter

End of Block interrupts (TXBEM, TXSEM, and

TXEOB bits in the S_ISR register).

1: Enable Transmitter Buffer Register Empty,

Transmitter Shift Register Empty, or Transmitter

End of Block interrupts.

Note: TXDI has no effect on DMA transfers.

BSN

RXEOB TXEOB

RXE

RXA

RXB

RXDI

TXDI

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