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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7SUPERLITE датащи(PDF) 88 Page - STMicroelectronics |
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ST7SUPERLITE датащи(HTML) 88 Page - STMicroelectronics |
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88 / 122 page  ST7LITE0, ST7SUPERLITE 88/122 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 13.5.1 General Timings Notes: 1. Guaranteed by Design. Not tested in production. 2. Data based on typical application software. 3. Time measured between interrupt event and interrupt vector fetch. Dtc(INST) is the number of tCPU cycles needed to fin- ish the current instruction execution. Symbol Parameter 1 Conditions Min Typ 2) Max Unit tc(INST) Instruction cycle time fCPU=8MHz 2 3 12 tCPU 250 375 1500 ns tv(IT) Interrupt reaction time 3) tv(IT) = ∆tc(INST) + 10 fCPU=8MHz 10 22 tCPU 1.25 2.75 µs 1 |
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