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ST7263B датащи(PDF) 99 Page - STMicroelectronics |
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ST7263B датащи(HTML) 99 Page - STMicroelectronics |
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99 / 132 page ![]() ST7263B 99/132 OPERATING CONDITIONS (Cont’d) 13.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for VDD, fCPU, and TA. Refer to Figure 9 on page 17. Notes: 1. Not tested, guaranteed by design. 2. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production. Symbol Parameter Conditions Min Typ 1) Max Unit VIT+ Low Voltage Reset Threshold (VDD rising) VDD Max. Variation 50V/ms 3.6 3.7 3.8 V VIT- Low Voltage Reset Threshold (VDD falling) VDD Max. Variation 50V/ms 3.3 3.5 3.7 V Vhyst Hysteresis (VIT+ - VIT-) 180 200 220 mV VtPOR VDD rise time rate 2) 0.5 50 V/ms |
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