ST72589BW datasheet(29/158 Pages) STMICROELECTRONICS

29 / 158 page

ST72589BW, ST72389BW

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4.2 POWER SAVING MODES

4.2.1 Introduction

To give a large measure of flexibility to the applica-

tion in terms of power consumption, four main

power saving modes are implemented in the ST7.

After a RESET the normal operating mode is se-

lected by default (RUN mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

main oscillator frequency divided by 2 (fCPU).

From Run mode, the different power saving

modes may be selected by setting the relevant

instruction whose action depends on the oscillator

status.

Figure 17. Power saving mode consumption / transitions

4.2.2 HALT Modes

The HALT modes are the lowest power consump-

tion modes of the MCU. They are entered by exe-

cuting the ST7 HALT instruction (see Figure 19).

Two different HALT modes can be distinguished:

– HALT: main oscillator is turned off,

– ACTIVE-HALT: only main oscillator is running.

The decision to enter either in HALT or ACTIVE-

HALT mode is given by the main oscillator enable

interrupt flag (OIE bit in CROSS-MCCSR register:

see Table 9).

When entering HALT modes, the I1 and I0 bits in

the CC Register are forced to level 0 (“10”) to ena-

ble interrupts.

The MCU can exit HALT or ACTIVE-HALT modes

on reception of either an external interrupt, an in-

terrupt with Exit from Halt Mode capability or a re-

set (see Table 2). A 4096 CPU clock cycles delay

is performed before the CPU operation resumes

(see Figure 18).

After the start up delay, the CPU resumes opera-

tion by servicing the interrupt or by fetching the re-

set vector which woke it up.

Table 9. HALT Modes selection

Figure 18. HALT /ACTIVE-HALT Modes timing overview

POWER CONSUMPTION

WAIT

SLOW

RUN

HALT

ACTIVE-HALT

High

Low

SLOW WAIT

MCCSR

OIE

flag

Power Saving Mode entered when HALT

instruction is executed

HALT (reset if watchdog enabled)

ACTIVE-HALT (no reset if watchdog enabled)

HALT OR ACTIVE-HALT

RUN

4096 CPU CYCLE

DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

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