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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72589BW датащи(PDF) 115 Page - STMicroelectronics |
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ST72589BW датащи(HTML) 115 Page - STMicroelectronics |
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115 / 158 page  ST72589BW, ST72389BW 115/158 CONTROLLER AREA NETWORK (Cont’d) 7.8.3.3 Modes of Operation The CAN Core unit assumes one of the seven states described below: – STANDBY. Standby mode is entered either on a chip reset or on resetting the RUN bit in the Con- trol/Status Register (CSR). Any on-going trans- mission or reception operation is not interrupted and completes normally before the Bit Time Log- ic and the clock prescaler are turned off for mini- mum power consumption. This state is signalled by the RUN bit being read-back as 0. Once in standby, the only event monitored is the reception of a dominant bit which causes a wake- up interrupt if the SCIE bit of the Interrupt Control Register (ICR) is set. The STANDBY mode is left by setting the RUN bit. If the WKPS bit is set in the CSR register, then the controller passes through WAKE-UP otherwise it enters RESYNC directly. It is important to note that the wake-up mecha- nism is software-driven and therefore carries a significant time overhead. All messages received after the wake-up bit and before the controller is set to run and has completed synchronization are ignored. – WAKE-UP. The CAN bus line is forced to domi- nant for one bit time signalling the wake-up con- dition to all other bus members. Figure 63. CAN Controller State Diagram n STANDBY RESYNC WAKE-UP RECEPTION TRANSMISSION ERROR IDLE ARESET RUN RUN & WKPS RUN & WKPS FSYN & BOFF & 11 Recessive bits | (FSYN | BOFF) & 128 * 11 Recessive bits RUN Write to DATA7 | TX Error & NRTX Start Of Frame Arbitration lost TX Error RX Error TX OK RX OK BOFF BOFF |
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