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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72311R датащи(PDF) 134 Page - STMicroelectronics |
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ST72311R датащи(HTML) 134 Page - STMicroelectronics |
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134 / 164 page  ST72311R, ST72511R, ST72512R, ST72532R 134/164 OPERATING CONDITIONS (Cont’d) 12.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating condition for VDD,fOSC, and TA. Figure 68. LVD Threshold Versus V DD and f OSC for ROM devices 2) Notes: 1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested. 2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production. Symbol Parameter Condition s Min Typ 1) Max Unit VIT+ Reset release threshold (VDD rise) 3.95 4.15 4.35 V VIT- Reset generation threshold (VDD fall) 3.70 3.90 4.10 Vhyst LVD voltage threshold hysteresis VIT+-VIT- 250 mV VtPOR VDD rise time rate 2) 0.02 V/ms tg(VDD) Filtered glitch delay on VDD Not detected by the LVD 40 ns fOSC [MHz] SUPPLY VOLTAGE [V] 16 8 0 2.5 3 3.5 4 4.5 5 5.5 FUNCTI ONAL AREA DEVICE UNDER RESET IN THIS AREA FUNCTI ONALITY NOT GUARAN TEED IN THIS AREA VIT-≥3.70 |
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