ST72260G datasheet(158/171 Pages) STMICROELECTRONICS

158 / 171 page

ST72260G, ST72262G, ST72264G

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DEVICE CONFIGURATION (Cont’d)

OPT 0 = FMP_W

FLASH write protection

This option indicates if the FLASH program mem-

ory is write protected.

Warning: When this option is selected, the pro-

gram memory (and the option bit itself) can never

be erased or programmed again.

0: Write protection off

1: Write protection on

USER OPTION BYTE 1

OPT 7 = EXTIT

Port C External Interrupt Configu-

ration.

This option bit allows the Port C external interrupt

mapping to be configured as ei0 or ei1.

Table 26. External Interrupt Configuration

OPT 6 = CSS

Clock Security System on/off

This option bit enables or disables the clock secu-

rity system (CSS) which include the clock filter and

the backup safe oscillator.

0: CSS enabled

1: CSS disabled

Caution: The Clock Security System is not guar-

anteed. The features described in Section 6.4.3 on

page 26 are subject to revision.

OPT 5:4 = OSCTYPE[1:0]

Oscillator Type selec-

tion

These option bits select the Oscillator Type.

OPT 3:1 = OSCRNGE[2:0]

Oscillator Range se-

lection

These option bits select the oscillator range.

OPT 0 = PLL

PLL selection

This option bit selects the PLL which allows multi-

plication by two of the oscillator frequency. The

PLL must not be used with the internal RC oscilla-

tor. It is guaranteed only with a fOSC input frequen-

cy between 2 and 4MHz.

0: PLL x2 enabled

1: PLL x2 disabled

CAUTION: the PLL can be enabled only if the

“OSC RANGE” (OPT3:1) bits are configured to

“MP - 2~4MHz”. Otherwise, the device functionali-

ty is not guaranteed.

ei0

ei1

EXTIT

option

bit

PA[7:0] Ports

PB[7:0] Ports

PC[5:0] Ports

PA[7:0] Ports

PC[5:0] Ports

PB[7:0] Ports

Clock Source

OSCTYPE1 OSCTYPE0

Resonator Oscillator

Reserved

Internal RC Oscillator

External Source

Typ. Freq. Range

OSC

RNGE2

OSC

RNGE1

OSC

RNGE0

VLP 32~100kHz

1~2MHz

2~4MHz

4~8MHz

8~16MHz

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