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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72260G датащи(PDF) 125 Page - STMicroelectronics |
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ST72260G датащи(HTML) 125 Page - STMicroelectronics |
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125 / 171 page  ST72260G, ST72262G, ST72264G 125/171 OPERATING CONDITIONS (Cont’d) 13.3.2 Low Voltage Detector (LVD) Thresholds TA = -40 to +85°C unless otherwise specified Notes: 1. Data based on characterization results, not tested in production. 2. When VtPOR is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after VDD crosses the VIT+(LVD) threshold. Figure 65. LVD Startup Behaviour Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state. However, in some devices, the reset state is released when VDD is approximately between 0.8V and 1.5V. As a consequence, depending on the ramp-up speed, the I/Os may toggle when VDD is within this win- dow. This may be an issue especially for applications where the MCU drives power components. Because Flash write access is impossible within this window, the Flash memory contents will not be cor- rupted. Symbol Parameter Conditions Min Typ Max Unit VIT+(LVD) Reset release threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.0 1) 3.55 1) 2.95 1) 4.2 3.75 3.15 4.5 4.0 3.35 V VIT-(LVD) Reset generation threshold (VDD fall) High Threshold Med. Threshold Low Threshold 3.75 3.3 2.75 4.0 3.55 3.0 4.251) 3.751) 3.151) Vhys(LVD) LVD voltage threshold hysteresis VIT+(LVD)-VIT-(LVD) 150 200 250 mV VtPOR VDD rise time rate 1)2) 20 µs/V 100 ms/V tg(VDD) Filtered glitch delay on VDD 1) Not detected by the LVD 40 ns 5V 1.5V VIT+ 0.8V LVD RESET V D D Window t |
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