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ST62T15C датащи(PDF) 66 Page - STMicroelectronics

номер детали ST62T15C
подробное описание детали  8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
PDF  105 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST62T15C датащи(HTML) 66 Page - STMicroelectronics

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OPERATING CONDITIONS (Cont’d)
11.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for VDD, fOSC, and TA.
Notes:
1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
3. Data based on characterization results, not tested in production.
Figure 39. LVD Threshold Versus VDD and fOSC
3)
Figure 40. Typical LVD Thresholds Versus
Temperature for OTP devices
Figure
41.
Typical
LVD
thresholds
vs.
Temperature for ROM devices
Symbol
Parameter
Conditions
Min
Typ 1)
Max
Unit
VIT+
Reset release threshold
(VDD rise)
3.9
4.1
4.3
V
VIT-
Reset generation threshold
(VDD fall)
3.6
3.8
4
Vhys
LVD voltage threshold hysteresis
VIT+-VIT-
50
300
700
mV
VtPOR
VDD rise time rate
2)
mV/s
tg(VDD)
Filtered glitch delay on VDD
3)
Not detected by the LVD
30
ns
fOSC [MHz]
SUPPLY
8
4
0
2.5
3
3.5
4
4.5
5
5.5
FUNCTIONAL AREA
RESET
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
VIT-≥3.6
DEVICE UNDER
IN THIS AREA
6
VOLTAGE [V]
-40°C
25°C
95°C
125°C
T [°C]
3.6
3.8
4
4.2
Thresholds [V]
Vdd up
Vdd down
VIT+
VIT-
-40°C
25°C
95°C
125°C
T [°C]
3.6
3.8
4
4.2
Thresholds [V]
Vdd up
Vdd down
VIT+
VIT-
1



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