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ST52T400 датащи(PDF) 54 Page - STMicroelectronics

номер детали ST52T400
подробное описание детали  8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG
PDF  94 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
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ST52T400 датащи(HTML) 54 Page - STMicroelectronics

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8 WATCHDOG TIMER
8.1 Functional Description
The Watchdog Timer (WDT) is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which causes the application program
to abandon its normal sequence. The WDT circuit
generates an MCU reset on expiry of a pro-
grammed time period (Timeout), unless the pro-
gram refreshes the WDT before the end of the
programmed time period itself.
16 different time delays can be selected by using
the WDT configuration register REG_CONF2 as
in Table 8.2.
WDT is activated by the assembler instruction
WDTRFR
.
At the end of the programmed time delay, WDT
starts a reset cycle pulling the reset pin low.
During normal operation, when WDT is active, the
application program has to refresh this peripheral
at regular intervals to prevent an MCU reset. WDT
refresh is performed by the WDTRFR assembler
instruction.
To stop WDT during the user program executions
instruction WDTSLP has to be used.
WDT working frequency is equal to Master Clock
frequency divided by a fixed Prescaler with a divi-
sion factor of 500, to obtain WDT CLK signal that
is used to fix the WDT Timeout period (Figure
8.1).
With a Master Clock of 20MHz, for instance, a
WDT Timeout period can be defined between
0.025ms and 234.375ms, depending on WDT
REG_CONF2 values.
Timeout delay values at different Master Clock fre-
quencies can be calculated as the product of WDT
clock number pulses (Table 8.2) by WDT CLK
period (Table 8.4).
Warning: changing the REG_CONF2 value when
the WDT is active, a WDT reset is generated and
the CPU is restarted. To avoid this side effect, use
the WDTSLP instruction before changing the
REG_CONF2.
Table 8.1 Watchdog Timing range (CLKM=20
MHz)
WDT Timeout period (ms)
min
0.025
max
234.375
Figure 8.1 Watchdog Block Diagram
D0
D1
D2
D3
REG_CONF 2
RESET
WDTRFR
PRES CLK = CLK MASTER
WDTSLP
PRESCALER
WDT
RESET
GENERATOR
RESET
WTD CLK



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