------------------------------------------------------------------------------------------------------------------------
AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
------------------------------------------------------------------------------------------------------------------------
Unused terminals. Don't connect any lines to these terminals.
Open
3
NC
The following registers can be initialized by setting the RST
signal to low level.
1. On/off register 0 set (display off)
2. Display start line register line 0 set (displays from line 0)
After releasing reset, this condition can be changed only by
instruction.
CPU or
external CR
I
1
RST
Liquid crystal display column (segmnet) drive output.
These pins outputs light on level when 1 is in the display RAM,
and light off level when 0 is it.
Relation among output level, M, and display data (D) is as
follows:
M
D
Output
level
1
0
1
0
1
0
V1
V3
V2
V4
Liquid
crystal
display
O
64
Y1 - Y64
2-phase clock signal for internal operation.
The £ p1 and £ p
2 clocks are used to preform operations (I/O
of display data and execution of instructions) other than display.
AX6107
I
2
£ p1, £ p2
Synchronous signal to latch display data. The rising CL signal
increments the disiplay output address counter and latches the
display data.
AX6107
I
1
CL
Display synchronous signal (frame signal).
Presets the 6-bit display line counter and synchronizes the
common signal with the frame timing when the FRM signal
becomes high.
AX6107
I
1
FRM
Switch signal to convert liquid crystal drive wavefojrm into AC.
AX6107
I
1
M
Data bus, three-state I/O common terminal.
MPU
I/O
8
DB1 - DB7
Address control signal to determine the relation between Y
address of display RAM and terminals from which the data is
output.
ADC = High : Y1 : $0, Y64 : $63
ADC = Low : Y64 : $0, Y1 : $63
Vcc/GND
I
1
ADC
Functions
Connected
to
I/O
Number of
Terminals
Terminal
Name
Note : 1 corresponds to high level in positive logic.
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