ST24LC21B datasheet(16/22 Pages) STMICROELECTRONICS

16 / 22 page

BYTE WRITE

CONTROL

BYTE

WORD ADDR

DATA

PAGE WRITE

WORD ADD n

DATA n

DATA n + 1

AI01894

ACK

VCLK/WC

CONTROL

BYTE

DATA n + 7

ACK

Figure 12. Inhibited Write when VCLK/WC = 0

– Step 1: the Master issues a START condition

followed by a Device Select byte (1st byte of

the new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no ACK will be returned and the

master goes back to Step 1. If the memory

has terminated the internal write cycle, it will

respond with an ACK, indicating that the mem-

ory is ready to receive the second part of the

instruction (the first byte of this instruction was

already sent during Step 1).

Read Operations

On delivery, the memory content is set at all "1’s"

(or FFh).

Current Address Read. The memory has an inter-

nal byte address counter. Each time a byte is read,

this counter is incremented. For the Current Ad-

dress Read mode, following a START condition,

the master sends the Device Select code with the

RW bit set to ’1’. The memory acknowledges this

and outputs the data byte addressed by the internal

byte address counter. This counter is then incre-

mented. The master must NOT acknowledge the

data byte output and terminates the transfer with a

STOP condition.

Random Address Read. A dummy write is per-

formed to load the address into the address

counter, see Figure 14. This is followed by a Re-

START condition send by the master and the De-

vice Select code is repeated with the RW bit set to

’1’. The memory acknowledges this and outputs the

addressed data byte. The master must NOT ac-

knowledge the data byte output and terminates the

transfer with a STOP condition.

Sequential Read. This mode can be initiated with

either a Current Address Read or a Random Ad-

dress Read. However, in this case the master

DOES acknowledge the data byte output and the

memory continues to output the next byte in se-

quence. To terminate the stream of bytes, the

master must NOT acknowledge the last data byte

output, and MUST generate a STOP condition.

The output data is from consecutive byte ad-

dresses, with the internal byte address counter

automatically incremented after each byte output.

After a count of the last memory address, the

address counter will ’roll-over’ and the memory will

continue to output data.

Acknowledge in Read Mode. In all read modes

the ST24xy21 wait for an acknowledge during the

9th bit time. If the master does not pull the SDA line

16/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

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