L6591

Application information

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Figure 7.

Timing diagram showing short-circuit behavior

(SS pin clamped below 5 V)

5.2

Operation at no load or very light load

When the PWM control voltage at pin COMP falls below a threshold located at 1.75 V, the IC

is disabled with both the high-side and the low-side MOSFET kept in OFF-state, the

oscillator stopped and the quiescent consumption very much reduced to minimize Vcc

capacitor discharge.

The control voltage now will increase as a result of the feedback reaction to the energy

delivery stop and, as it exceeds 1.82 V, the IC will restart switching. After a while, the control

voltage will go down again in response to the energy burst and stop the IC. In this way the

converter will work in a burst-mode fashion with a nearly constant peak current. A further

load decrease will then cause a frequency reduction, which can go down even to few

hundred hertz, thus minimizing all frequency-related losses and making it easier to comply

with energy saving regulations. The timing diagram of Figure 8 illustrates this kind of

operation, showing the most significant signals.

If it is necessary to decrease the intervention threshold of the burst-mode operation, this can

be done by adding a small DC offset on the current sense pin as shown in Figure 9.

Note: The offset reduces the available dynamics of the current signal; thereby, the value of

the sense resistor must be determined taking this offset into account.

 

Vcc

LVG,HVG

Vcc_OK