6

Simtek Confidential

Jan, 2008

Document Control #ML0060 Rev 1.1

STK14EC8

Preliminary

SRAM WRITE CYCLES #1 & #2

Note g:

If W is low when E goes low, the outputs remain in the high-impedance state.

Note h:

E or W must be

≥ V

NO.

SYMBOLS

PARAMETER

STK14EC8-15

STK14EC8-25

STK14EC8-45

UNITS

#1

#2

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

12

Write Cycle Time

15

25

45

ns

13

Write Pulse Width

10

20

30

ns

14

Chip Enable to End of Write

15

20

30

ns

15

Data Set-up to End of Write

5

10

15

ns

16

Data Hold after End of Write

0

0

0

ns

17

Address Set-up to End of Write

10

20

30

ns

18

Address Set-up to Start of Write

0

0

0

ns

19

Address Hold after End of Write

0

0

0

ns

20

e, g

Write Enable to Output Disable

7

10

15

ns

21

Output Active after End of Write

3

3

3

ns

PREVIOUS DATA

DATA OUT

E

ADDRESS

12

W

16

DATA IN

19

13

18

17

DATA VALID

20

15

HIGH IMPEDANCE

21

14

DATA IN

12

16

13

19

18

17

DATA VALID

15

HIGH IMPEDANCE

14

DATA OUT

E

ADDRESS

W

DATA IN