ST1305B

2/2

wise fashion for reading and programming, and in

a byte-wise fashion for internal erasing.

The device recognises three commands issued

via the RST and CLK pins (as described in the full

data sheet):

– RESET: to reset the internal address register to

00d

– READ: to increment the internal address regis-

ter, and read the data bit at that address

– PROG: to program the bit at the current ad-

dress.

The device offers two distinct configurations:

– ISSUER: for the card manufacturer, allowing

special data to be written to the chip, during ini-

tialisation

– USER: for the end user of the card, restricting

access to the chip.

Before delivery, from ST to the card issuer, the de-

vice is placed in the ISSUER configuration. This

operation is performed by blowing the “test fuse”.

Figure 2. Memory Map

DS05B07

128d

192d

Issuer Defined Area

READ

ONLY

In USER Configuration

64 bits

Circuit Identification

000d

016d

064d

112d

READ

ONLY

Card Identification

Counters / Transport Code

Certificate

16 bits

EEPROM

Cells

Matrix

48 bits

48 bits

Unused

Fuses

260d

16 bits

READ, WRITE,

ERASE

Table 2. Ordering Information Scheme

Example:

ST1305B

-

W4

/

XX

YY

Delivery Form

Transport Code

D10

Micromodule on Super 35 mm reel

Given by ST

D15

Micromodule on Super 35 mm reel

W4

Wafer (180

µm thickness)

Customer Code

Given by the Issuer