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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST10F269 датащи(PDF) 113 Page - STMicroelectronics |
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ST10F269 датащи(HTML) 113 Page - STMicroelectronics |
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113 / 160 page  ST10F269 113/160 Figure 59 : Minimum External Reset Circuitry Figure 60 : External Reset Hardware Circuitry Table 29 : PORT0 Latched Configuration for the Different Resets Notes: 1. Not latched from PORT0. 2. Only RP0H low byte is used and the bit-fields are latched from PORT0 high byte to RP0H low byte. 3. Indirectly depend on PORT0. 4. Bits set if EA pin is 1. X : Pin is sampled - : Pin is not sampled PORT0 Sample event Software Reset - - - X X X X X X X - - - - - - Watchdog Reset - - - X X X X X X X - - - - - - Short Hardware Reset - - - X X X X X X X X X X X X X Long Hardware Reset XXX XX XXX XX XXX XX X Power-On Reset X X X X X X X X X X X X X X X X Table 30 : PORT0 Bits Latched into the Different Registers After Reset PORT0 bit nber h7 h6 h5 h4 h3 h2 h1 h0 I7 I6 I5 I4 I3 I2 I1 I0 PORT0 bit Name CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BUSTYP BUSTYP R BSL R R ADP EMU RP0H 2 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC SYSCON X 1 X 1 X 1 X 1 X 1 X 1 BYTDIS 3 X 1 WRCFG 3 X 1 X 1 X 1 X 1 X 1 X 1 X 1 BUSCON0 X 1 X 1 X 1 X 1 -BUS ACT0 4 ALE CTL0 4 -BTYP BTYP X 1 X 1 X 1 X 1 X 1 X 1 Internal Logic To Clock Generator To Port 4 Logic To Port 6 Logic X 1 X 1 X 1 X 1 Internal X 1 X 1 Internal Internal + + RSTOUT RSTIN RPD C0 R0 VDD C1 External Hardware ST10F269 a) Manual hardware reset1 b) For automatic power-up and a) b) interruptible power-down mode D2 RSTOUT RSTIN RPD Open - drain D1 + C0 R0 VDD ST10F269 VDD External Hardware Inverter + C1 R1 VDD Reset Source External R2 |
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