ST10F269 datasheet(110/160 Pages) STMICROELECTRONICS

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ST10F269

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The short hardware reset ends and the MCU restarts.To be processed as a short hardware reset, the

external RSTIN signal must last a maximum of 1038 TCL (4 TCL + 10 TCL + 1024 TCL). The system

configuration is latched from PORT0 after a duration of 8 TCL / 4 CPU clocks (6 TCL / 3 CPU clocks if PLL

is bypassed) and in case of external fetch, ALE, RD and R/W pins are driven to their inactive level.

Program execution starts from memory location 00'0000h in code segment 0. This starting location will

typically point to the general initialization routine.

Timings of synchronous reset sequence are

summarized in Figure 57. Refer to Table 29 for PORT0 latched configuration.

Note

- If the RSTIN pin level is sampled low, the reset sequence is extended until RSTIN level becomes

high leading to a long hardware reset (synchronous or asynchronous reset) because RSTIN

signal duration has lasted longer than 1040TCL.

- If the VRPD voltage has droped below the RPD pin threshold, the reset is processed as an

asynchronous reset.

Figure 57 : Synchronous Warm Reset Sequence External Fetch (4 TCL < RSTIN pulse < 1038 TCL)

Note

1) RSTIN assertion can be released there.

2) Maximum internal synchronisation is 6 CPU cycles (12 TCL).

3) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after

reset.

4) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on

(fCPU =fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).

5) If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (typically 2.5V for 5V operation), the

ST10 reset circuitry disables the bidirectional reset function and RSTIN pin is no more pulled low.

18.3 - Software Reset

The reset sequence can be triggered at any time using the protected instruction SRST (software reset).

This instruction can be executed deliberately within a program, for example to leave bootstrap loader

mode, or upon a hardware trap that reveals a system failure.

Upon execution of the SRST instruction, the internal reset sequence (1024 TCL) is started. The

microcontroller behavior is the same as for a short hardware reset, except that only P0.12...P0.6 bits are

latched at the end of the reset sequence, while previously latched values of P0.5...P0.2 are cleared.

18.4 - Watchdog Timer Reset

When the watchdog timer is not disabled during the initialization or when it is not regularly serviced during

program execution it will overflow and it will trigger the reset sequence.

CPU Clock

RSTIN

RPD

RSTOUT

ALE

PORT0

1st Instr.

Latching point of PORT0

for system start-up configuration

6 or 8 TCL4)

4 TCL 10 TCL

min.

1024 TCL

Reset Configuration

If VRPD > 2.5V Asynchronous

200

µA Discharge

6789

Reset is not entered.

Internal reset signal

Internally pulled low 3)

5 TCL

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