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NOT FOR NEW DESIGN

November 2002

This is information on a product still in production but not recommended for new designs.

SSM1105V

Scalar System Memory (SSM)

for Image Processor ICs

FEATURES SUMMARY

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System solution for use with image processing

scalar ICs

– For LCD monitors, projectors, and TVs

– Compatible with Pixelworks PW11x/PWx64

families (and similar image processors or mi-

cro-controllers)

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Single integrated package, including:

– Dual bank Flash memories

– General purpose I/O

– Programmable logic

– In-System Programming via JTAG

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Dual bank Flash memories

– Provide concurrent operation

– 5 Mbit main Flash memory

– 384 Kbit secondary Flash memory (divided

into 10 small sectors)

– Programmable Decode PLD for flexible ad-

dress mapping of both memories

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Dual Display Data Channels (DDC)

– Supports DDC for both analog RGB and digi-

tal DVI video input channels

– DDC1/DDC2B VESA standard compliant

– 256 byte SRAM buffer for each DDC channel

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– Each capable of master or slave operation

– Control A/D converters, video decoders, and

future devices (tuner, audio, etc.)

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Four Pulse Width Modulator (PWM) channels

– 16-bit resolution for period and for duty cycle

– 16-bit clock prescalers

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Seven I/O ports with 52 I/O pins for Multifunction

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3000 gate PLD with 16 macrocells, for creating

glue logic, state machines, clock dividers,

decoders, chip-selects, inverters; and to

Figure 1. Packages

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In-System Programming (ISP) with JTAG

– Program entire chip in 30-40 seconds with no

involvement of the processor

– Program with low-cost FlashLINK

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Content Security: Programmable Security Bit

blocks access of device programmers / readers

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Zero-Power Technology: memory and PLD

blocks automatically switch to stand-by current

between input changes

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Package and Specifications

– 100-pin TQFP, 14 x 14mm

– 90 ns memory access time

TQFP100 (U)