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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD511B1 датащи(PDF) 110 Page - STMicroelectronics |
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PSD511B1 датащи(HTML) 110 Page - STMicroelectronics |
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110 / 153 page  PSD5XX Family 107 System Configuration (Cont.) Register Name Register Function PAGE REGISTER A 4-bit register that supports paging. INTR. READ Reading this register clears all the pending edge sensitive CLEAR interrupts. INTR. Define interrupt input as level or edge sensitive. EDGE/LEVEL INTR. MASK Mask selected interrupt input. INTR. A “1” in the register indicates the corresponding interrupt is REQUEST LATCH pending. INTR. The register indicates which pending interrupt has the highest PRIORITY STATUS priority. 1. Configures the PSD SRAM to be accessed by “PSEN” as VM program space (8031 design). 2. Enable the Peripheral I/O Mode of Port A. PMMR0 Power management registers; enable the PSD Power Down Mode PMMR1 and other power saving configurations. STATUS FLAGS Counter/Timer Freeze Acknowledge bits. GLOBAL Specifies the Counter/Timer operation mode; and to start or stop COMMAND the Counter/Timers. DLCY Specifies the delay cycles to the Counter/Timers. SOFTWARE This register enables a load (to the Counter/Timer) or store LOAD/STORE (in the Image Register) operation. FREEZE This register disables the timer state-machine before access to the COMMAND Image Register is allowed. CMD3 – 0 Command Registers for the configuration of the Counter/Timers. CNTR3 – 0 The four 16-bit Counter/Timers. IMG3 – 0 The Image Registers for CNTR3 – 0. Table 33. Other Register Function |
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