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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD511B1 датащи(PDF) 92 Page - STMicroelectronics |
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PSD511B1 датащи(HTML) 92 Page - STMicroelectronics |
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92 / 153 page  PSD5XX Family 89 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 **** FrezAck3 FrezAck2 FrezAck1 FrezAck0 NOTES: At RESET all these bits intialize as 0's. * = Not used. 9.6.2.6 Status Flags Register There are eight READ-ONLY status flags. The lower four bits represent Freeze Acknowledge bits. Counter/Timer Registers (Cont.) FrezAck Bits These Freeze Acknowledge bits are useful in the Freeze/Freeze Acknowledge protocol. After the Microcontroller senses that the FrezAck bit is being set it proceeds to access the Image Register for a read or write operation. FrezAck0 Bit: When this bit is 1: Image Register Access is granted. 0: Image Register Access is not granted. FrezAck1 Bit: When this bit is 1: Image Register Access is granted. 0: Image Register Access is not granted. FrezAck2 Bit: When this bit is 1: Image Register Access is granted. 0: Image Register Access is not granted. FrezAck3 Bit: When this bit is 1: Image Register Access is granted. 0: Image Register Access is not granted. DLCY Register: Bits <4:0> of the DLCY register are used to assign Delay Cycles to the Counter/Timer. Various Clock Scaling values possible are 0 through 31 (decimal). At RESET these bits initialize as 0. If necessary, the user has the option to set these bits up to generate Delay Cycles (DLCY) to scale down the Counter/Timer clock (see Table 24). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ** * DLCY4 DLCY3 DLCY2 DLCY1 DLCY0 NOTE: * = Not used. |
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