PSD511B1 datasheet(101/153 Pages) STMICROELECTRONICS

101 / 153 page

PSD5XX Family

Interrupt Operation (Cont.)

9.7.1.1 Command Registers

All the eight interrupts can be individually masked using a mask register. Writing “ones”

into these mask bits enables the associated interrupts. RESET masks all interrupts.

Interrupts can also be defined as either LEVEL sensitive or EDGE sensitive using a

sensitivity bit in the interrupt edge/level sensitivity select register.

Tables 29 and 29a give the address map for various port and interrupt Command/Status

Registers. This address offset map is of the host processor, relative to the CSIOP

(Chip Select Input Output Port) i.e., address space allocated by the host Microcontroller to

access all the PSD embedded peripherals.

Address

Offset

+D4h

Interrupt Read Clear

+D3h

Interrupt Mask

+D2h

Interrupt Edge/Level

Select

+D1h

Interrupt Request Latch

+D0h

Interrupt Priority Status

Table 29. Offset Address Map of Interrupt Registers

Address

Offset

+D5h

Interrupt Read Clear

+D2h

Interrupt Mask

+D3h

Interrupt Edge/Level

Select

+D0h

Interrupt Request Latch

+D1h

Interrupt Priority Status

Table 29a. Offset Address Map of Interrupt Registers

(For 16-Bit Motorola MCUs in 16-Bit Mode. If 8-Bit Mode is selected, use Table 29.)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mask7

Mask6

Mask5

Mask4

Mask3

Mask2

Mask1

Mask0

Interrupt Mask Register

Bits mask 0

... mask 7 correspond to interrupt 0 ... interrupt 7.

When these bits are set to

1 = Unmasked

0 = Masked

At RESET these bits initialize as 0 and all interrupts are masked.

The Interrupt Registers listed in Tables 29 and 29a are described below.

Interrupt

Controller

(Cont.)

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