ADATE320KCPZ datasheet(26/78 Pages) AD

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Data Sheet

ADATE320

ABSOLUTE MAXIMUM RATINGS

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Rev. C | 26 of 78

2 See Figure 138 for more detailed information about high speed DATx/RCVx input multiplexing.

Table 18. Comparator Truth Table

DMC_ENABLE, Address

0x1A, Bit 0

Comparator State

CMPH0

State

CMPL0

State

CMPH1

State

CMPL1

State

VDUT0 < VOH0

VDUT0 < VOL0

VDUT1 < VOH1

VDUT1 < VOL1

VOH0 < VDUT0

VOL0 < VDUT0

VOH1 < VDUT1

VOL1 < VDUT1

VDUT0 − VDUT1 < VOH0

VDUT0 − VDUT1 < VOL0

VDUT1 < VOH1

VDUT1 < VOL1

VOH0 < VDUT0 − VDUT1

VOL0 < VDUT0 − VDUT1

VOH1 < VDUT1

VOL1 < VDUT1

1 Note that the Channel 1 normal window comparator continues to function while the device is in differential compare mode, but at a greatly reduced bandwidth.

Table 19. Active Load Truth Table

LOAD/DRV Control Registers1

High Speed Inputs2

Load State

LOAD_ENABLE_x,

Address 0x1B, Bit 0

LOAD_FORCE_x,

Address 0x1B, Bit 1

DRIVE_VT_HIZ_x, Address 0x19, Bit 4

DATx

RCVx

Low leakage

Active on

Active off

Active on

Active off

1 X means don’t care.

2 See Figure 138 for more detailed information about high speed DATx/RCVx input multiplexing.

Table 20. PPMU Go/No-Go Comparator Truth Table

PPMU Control Register1

PPMU Go/No-Go Comparator State2

PPMU_ENABLE_x, Address

0x1C, Bit 0

PPMU_STANDBY_x, Address

0x1C, Bit 1

PPMU_CMPHx

State

PPMU_CMPLx

State

PPMUx MV/MI < POHx

PPMUx MV/MI < POLx

POHx < PPMUx MV/MI

POLx < PPMUx MV/MI

1 X means don’t care.

2 The PPMUx MV/MI inputs to the PPMU go/no-go comparators always come directly from the respective internal PPMU instrumentation amplifiers, not from the PPMU_Mx

output pins (see Figure 143). The internal instrumentation amplifiers are independently configured for either measure voltage (MV) or measure current (MI), depending on

the settings of the PPMU_MEAS_VI_x control bit, as described in Figure 150. When PPMU power is not enabled, the respective go/no-go comparator outputs are locked to

a static low state (see Table 21).

Table 21. PPMU Measure Pin Truth Table

PPMU Control Register1

PPMU_Mx, Pin

State

PPMU_ENABLE_x,

Address 0x1C, Bit 0

PPMU_STANDBY_x,

Address 0x1C, Bit 1

PPMU_MEAS_ENABLE_x,

Address 0x1C, Bit 13

PPMU_MEAS_SEL_x,

Address 0x1C, Bit 14

PPMU_MEAS_VI_x,

Address 0x1C, Bit 6

High-Z

Active MV

Active VTHERM2

Active MV

Active MI

Active VTHERM2

1 X means don’t care.

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