Nexperia

74HCS32

Quad 2-input OR gate with Schmitt-trigger inputs

4. Functional diagram

A

B

Y

aaa-043593

Fig. 1. Logic diagram (one gate)

mna242

1A

1B

1Y

2

1

3

2A

2B

2Y

5

4

6

3A

3B

3Y

10

9

8

4A

4B

4Y

13

12

11

Fig. 2. Logic symbol

mna243

3

≥1

≥1

≥1

≥1

2

1

6

5

4

8

10

9

11

13

12

Fig. 3. IEC logic symbol

5. Pinning information

5.1. Pinning

1A

VCC

1B

4B

1Y

4A

2A

4Y

2B

3B

2Y

3A

GND

3Y

aaa-036070

1

2

3

4

5

6

7

8

10

9

12

11

14

13

D package

SOT108-1 (SO14)

1A

VCC

1B

4B

1Y

4A

2A

4Y

2B

3B

2Y

3A

GND

3Y

aaa-036071

1

2

3

4

5

6

7

8

10

9

12

11

14

13

PW package

SOT402-1 (TSSOP14)

aaa-036072

Transparent top view

2Y

3A

2B

3B

2A

4Y

1Y

4A

1B

4B

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

BQ package

SOT762-1 (DHVQFN14)

GND(1)

(1) This is not a ground pin. There is no electrical or mechanical requirement to solder

the pad. In case soldered, the solder land should remain floating or connected to GND.

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1A, 2A, 3A, 4A

1, 4, 9, 12

data inputs

1B, 2B, 3B, 4B

2, 5, 10, 13

data inputs

1Y, 2Y, 3Y, 4Y

3, 6, 8, 11

data outputs

GND

7

ground (0 V)

VCC

14

supply voltage

74HCS32

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© Nexperia B.V. 2025. All rights reserved

Product data sheet

Rev. 1 — 27 June 2025

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