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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LTC1860CS8 датащи(PDF) 3 Page - Linear Technology |
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LTC1860CS8 датащи(HTML) 3 Page - Linear Technology |
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3 / 12 page  3 LTC1860/LTC1861 18601f The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted. TA = 25°C. VCC = 5V, fSAMPLE = 250kHz, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio 72 dB S/(N + D) Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal 71 dB THD Total Hamonic Distortion Up to 5th Harmonic 100kHz Input Signal 77 dB Full Power Bandwidth 20 MHz Full Linear Bandwidth S/(N + D) ≥ 68dB 125 kHz DY A IC ACCURACY DIGITAL A D DC ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. RECO E DED OPERATI G CO DITIO S SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIH High Level Input Voltage VCC = 5.25V q 2.4 V VIL Low Level Input Voltage VCC = 4.75V q 0.8 V IIH High Level Input Current VIN = VCC q 2.5 µA IIL Low Level Input Current VIN = 0V q – 2.5 µA VOH High Level Output Voltage VCC = 4.75V, IO = 10µA q 4.5 4.74 V VCC = 4.75V, IO = 360µA q 2.4 4.72 V VOL Low Level Output Voltage VCC = 4.75V, IO = 1.6mA q 0.4 V IOZ Hi-Z Output Leakage CONV = VCC q ±3 µA ISOURCE Output Source Current VOUT = 0V – 25 mA ISINK Output Sink Current VOUT = VCC 20 mA IREF Reference Current (LTC1860 SO-8, MSOP and CONV = VCC q 0.001 3 µA LTC1861 MSOP) fSMPL = fSMPL(MAX) q 0.05 0.1 mA ICC Supply Current CONV = VCC After Conversion q 0.001 3 µA fSMPL = fSMPL(MAX) q 0.85 1.3 mA PD Power Dissipation fSMPL = fSMPL(MAX) 4.25 mW SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC Supply Voltage 4.75 5.25 V fSCK Clock Frequency q DC 20 MHz tCYC Total Cycle Time 12 • SCK + tCONV µs tSMPL Analog Input Sampling Time LTC1860 12 SCK LTC1861 10 SCK tsuCONV Setup Time CONV ↓ Before First SCK↑, 30 ns (See Figure 1) thDI Holdtime SDI After SCK ↑ LTC1861 15 ns tsuDI Setup Time SDI Stable Before SCK ↑ LTC1861 15 ns tWHCLK SCK High Time fSCK = fSCK(MAX) 40% 1/fSCK tWLCLK SCK Low Time fSCK = fSCK(MAX) 40% 1/fSCK tWHCONV CONV High Time Between Data tCONV µs Transfer Cycles tWLCONV CONV Low Time During Data Transfer 12 SCK thCONV Hold Time CONV Low After Last SCK ↑ 13 ns |
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