ADG526A/ADG527A

Rev. C | Page 13 of 20

TIMING

Figure 13 shows the timing sequence for latching the switch

address and enable inputs. The latches are level sensitive;

therefore, while WR is held low, the latches are transparent and

the switches respond to the address and enable inputs. This

input data is latched on the rising edge of WR.

3V

0V

3V

0V

WR

EN, A0, A1,

A2, (A3)

1.5V

2.0V

0.8V

Figure 13. Timing Sequence

Note that all digital input signal rise and fall times are measured

3V

0V

0V

RS

0.8V

1.5V

SWITCH

OUTPUT

Figure 14. Reset Pulse