PIC24FJ64GA006 datasheet(4/10 Pages) MICROCHIP

4 / 10 page

PIC24FJ128GA010

DS80330A-page 4

16. Module: SPI

In SPI Slave mode (MSTEN = 0), with the slave

select option enabled (SSEN = 1), the peripheral

may accept transfers regardless of the SSx pin

state. The received data in SSPxBUF will be

accurate but not intended for the device.

Work around

If the Slave select option is required (e.g., device

one of multiple SPI slave nodes on an SPI

network), two potential work arounds exist:

1. Configure the port associated with SSx to an

input and periodically read the PORT register. If

the pin is read ‘0’, disable the SPI peripheral

(SPIEN = 0). Enable the peripheral (SPIEN = 1)

if the pin is read as a logic ‘1’.

2. Read the pin associated with SSx after a trans-

fer is complete, indicated by the SPIxF bit

being set. If the port pin is read as a digital ‘1’,

read SSPxBUF and discard the contents.

Date Codes that pertain to this issue:

All engineering and production devices.

17. Module: Oscillator

The Two-Speed Start-up feature may not be

available on exit from Sleep mode with the IESO

(Internal/External Switchover mode) enabled.

Upon wake-up, the device will wait for the clock

source used prior to entering Sleep mode to

become ready.

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

18. Module: Core

The CLKDIV register Reset value is incorrect. The

‘1’ for all Resets.

Work around

Mask out unimplemented bits to maintain software

compatibility with future device revisions.

Date Codes that pertain to this issue:

All engineering and production devices.

19. Module: Core

If a clock failure occurs when the device is in Idle

mode, the oscillator failure trap does not vector to

the Trap Service Routine. Instead, the device will

simply wake-up from Idle mode and continue code

execution if the Fail-Safe Clock Monitor (FSCM) is

enabled.

Work around

Whenever the device wakes up from Idle (assum-

ing the FSCM is enabled), the user software

should check the status of the OSCFAIL bit

(INTCON1<1>) to determine whether a clock fail-

ure occurred and then perform an appropriate

clock switch operation.

Date Codes that pertain to this issue:

All engineering and production devices.

20. Module: Core

On a Brown-out Reset, both the BOR and POR

bits may be set. This may cause the Brown-out

Reset condition to be indistinguishable from the

Power-on Reset.

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

21. Module: Ports

RC15 may output a digital ‘0’ after a Reset until the

Configuration Word settings are processed. The

duration of time for this effect is TRST which is

nominally 20 µs.

After the Configuration Word is processed, RC15

is put into its reset state as a digital input.

Work around

Connect components not adversely affected by a

digital 0 signal to RC15.

Date Codes that pertain to this issue:

All engineering and production devices.

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