MPC8349E_07 datasheet(5/88 Pages) FREESCALE

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MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Overview

— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)

•

Universal serial bus (USB) multi-port host controller

— Can operate as a stand-alone USB host controller

– USB root hub with one or two downstream-facing ports

– Enhanced host controller interface (EHCI) compatible

– Complies with USB Specification Rev. 2.0

— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

— Direct connection to a high-speed device without an external hub

— External PHY with serial and low-pin count (ULPI) interfaces

•

Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 133 MHz

— Four chip selects support four external slaves

— Up to eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller

— Three protocol engines on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user-programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

•

Programmable interrupt controller (PIC)

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for 8 external and 35 internal discrete interrupt sources

— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources

— Programmable highest priority request

— Four groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Redirects interrupts to external INTA pin in core disable mode.

— Unique vector number for each interrupt source

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Dual industry-standard I2C interfaces

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

— System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded

hardware

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DMA controller

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