PSD813F2 datasheet(92/110 Pages) STMICROELECTRONICS

92 / 110 page

PSD835G2

PSD8XX Family

-90

-12

Symbol

Parameter

Conditions

Min

Max

Min

Max

Unit

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 1)

tLXAX

Address Hold Time

(Note 1)

tAVWL

Address Valid to Leading

Edge of WR

(Notes 1 and 3)

t SLWL

CS Valid to Leading Edge of WR

(Note 3)

t DVWH

WR Data Setup Time

(Note 3)

t WHDX

WR Data Hold Time

(Notes 3 and 7)

t WLWH

WR Pulse Width

(Note 3)

tWHAX1

Trailing Edge of WR to Address Invalid

(Note 3)

tWHAX2

Trailing Edge of WR to DPLD Address

(Notes 3 and 6)

Input Invalid

tWHPV

Trailing Edge of WR to Port Output

Valid Using I/O Port Data Register

(Note 3)

tWLMV

WR Valid to Port Output Valid Using

Micro

⇔Cell Register Preset/Clear

(Notes 3 and 4)

tDVMV

Data Valid to Port Output Valid

Using Micro

⇔Cell Register Preset/Clear

(Notes 3 and 5)

tAVPV

Address Input Valid to Address

(Note 2)

Output Delay

Write Timing (3.0 V to 3.6 V Versions)

NOTES: 1. Any input used to select an internal PSD835G2 function.

2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.

3. WR timing has the same timing as E and DS signals.

4. Assuming data is stable before active write signal.

5. Assuming write is active before data becomes valid.

6. tWHAX2 is Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.

tWHDX is 11ns when writing to the Output Micro⇔Cell Registers AB and BC.

Microcontroller Interface – PSD835G2 AC/DC Parameters

(3.0 V to 3.6 V Versions)

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