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AS5130ATST датащи(PDF) 24 Page - ams AG |
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AS5130ATST датащи(HTML) 24 Page - ams AG |
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24 / 41 page ![]() www.austriamicrosystems.com Revision 1.00 24 - 41 AS5130 Data Sheet - D e ta i l e d D e s c r i p t i o n If the AS5130 is cycled between active and reduced current mode, a substantial reduction of the average supply current can be achieved. The minimum dwelling time in active mode is the wake-up time. The actual active time depends on how much the magnet has moved while the AS5130 was in reduced power mode. The angle data is valid, when the status bit LOCK has been set (see Table 9). Once a valid angle has been measured, the AS5130 can be put back to reduced power mode. The average power consumption can be calculated as: Iavg = sampling interval = ton + toff (EQ 7) Where: Iavg = Average current consumption Iactive = Current consumption in active mode Ipower_down = Current consumption in reduced power mode ton = Time period during which the chip is operated in active mode toff = Ttime period during which the chip is in reduced power mode Reducing Power Supply Peak Currents An optional RC-filter (Rx/Cx) may be added to avoid peak currents in the power supply line when the AS5130 is toggled between active and reduced power mode. Rx must be chosen such that it can maintain a VDD voltage of 4.5 – 5.5V under all conditions, especially during long active periods when the charge on Cx has expired. Cx should be chosen such that it can support peak currents during the active operation period. For long active periods, Cx should be large and Rx should be small. Power Cycling Mode The power cycling method shown in Figure 17 cycles the AS5130 by switching it on and off, using an external PNP transistor high side switch. The current consumption in off-mode is zero. It also has the longest start-up time of all modes, as the chip must always perform a “cold start “ from zero, which takes about 1.9 ms (Compare with Low Power Mode on page 23). Figure 17. Power Cycling Mode The optional filter Rx/Cx may again be added to reduce peak currents in the 5V power supply line (see Reducing Power Supply Peak Currents on page 24). Polling Mode Target of this mode is a reduction of the average power consumption. In this mode, the IC supply is pulsed, thereby reducing the average power consumption to a fraction. The actual angle information and multi turn count value is not lost; polling mode is especially suited for battery powered applications. The IC is furthermore capable of generating a WAKE signal as soon as the magnet’s position has changed, but only if the supply of the IC is powered-on again. By means of the WAKE signal, the system’s power consumption can be further decreased, if certain modules are activated on demand. Iactive∗ton Ipowerdown∗toff + ton toff + --------------------------------------------------------------------- VDD VSS micro controller AS5130 100n VSS +5V VDD CS VDD DCLK DIO VSS AS5130 C1 S N Ion 0 ton toff on/off Rx 10k ton toff Cx >µF |
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