S2-LPS datasheet(51/73 Pages) STMICROELECTRONICS

номер детали	S2-LPS

подробное описание детали	Ultra-low power, high performance, sub-1 GHz transceiver

PDF	73 Pages

Scroll/Zoom	100%

производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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51 / 73 page

Name

Addr

Default

Bit

Field name

Description

CLOCKREC2

•

1: PLL.

3:0

CLK_REC_I_GAIN_S

LOW

Set the integral slow

gain for symbol timing

recovery (PLL mode

only).

CLOCKREC1

7:5

CLK_REC_P_GAIN_F

AST

Clock recovery fast

loop gain (log2).

PSTFLT_LEN

Select the post filter

length:

•

0: 8 symbols

•

1: 16 symbols.

3:0

CLK_REC_I_GAIN_F

AST

Set the integral fast

gain for symbol timing

recovery (PLL mode

only).

PCKTCTRL6

7:2

SYNC_LEN

The number of bits

used for the SYNC

field in the packet.

1:0

PREAMBLE_LEN[9:8]

The MSB of the

number of '01 or '10'

of the preamble of the

packet.

PCKTCTRL5

7:0

PREAMBLE_LEN[7:0]

The LSB of the

number of '01 or '10'

of the preamble of the

packet.

PCKTCTRL4

LEN_WID

The number of bytes

used for the length

field:

•

0: 1 byte

•

1: 2 bytes.

6:4

RESERVED

ADDRESS_LEN

1: include the

ADDRESS field in the

packet.

2:0

RESERVED

PCKTCTRL3

7:6

PCKT_FRMT

Format of packet:

•

0: Basic

•

1: 802.15.4g

•

2: UART OTA

•

3: Stack

(see

Section 6 Packet

handler engine)

5:4

RX_MODE

RX mode:

•

0: normal mode

•

1: direct through

FIFO

•

2: direct through

GPIO

FSK4_SYM_SWAP

Reserved

S2-LPS

DS13831 - Rev 1

page 51/73

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