PCF8534A datasheet(21/41 Pages) NXP

21 / 41 page

PCF8534A_0

Product data sheet

Rev. 00.90 — 4 February 2008

21 of 41

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

Basic architecture

8.1 Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer is initiated only when the bus is not busy.

8.1.1 Bit transfer

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the HIGH period of the clock pulse as

changes in the data line at this time will be interpreted as a control signal. Bit transfer is

illustrated in Figure 12.

8.1.1.1

START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change

of the data line, while the clock is HIGH, is defined as the START condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP

condition (P). The START and STOP conditions are illustrated in Figure 13.

8.1.2 System configuration

A device generating a message is a ‘transmitter’, a device receiving a message is the

‘receiver’. The device that controls the message is the ‘master’ and the devices which are

controlled by the master are the ‘slaves’. The system configuration is illustrated in

Figure 14.

Fig 12. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 13. Definition of START and STOP conditions

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

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