RZSLASHT1 datasheet(60/139 Pages) RENESAS

60 / 139 page

R01DS0228EJ0200 Rev.2.00

Page 60 of 139

Jun. 30, 2025

RZ/T1 Group

2. Electrical Characteristics

2.4

AC Characteristics

 Conditions: VDD = PLLVDD0 = PLLVDD1 = DVDD_USB = 1.14 to 1.26 V,

VCCQ33 = AVCC0 = AVCC1 = VREFH0 = VREFH1 = VDD33_USB = 3.0 to 3.6 V

VSS = PLLVSS0 = PLLVSS1 = AVSS0 = AVSS1 = VREFL0 = VREFL1 = VSS_USB = 0 V,

Tj = -40 to 125°C

Note:

The 176-pin HLFQFP does not have pins AVCC1, AVSS1, VREFH1, and VREFL1.

Note 1. For R7S910007CBG, R7S910107CBG, R7S910013CBG, R7S910113CBG, R7S910017CBG, R7S910117CBG,

R7S910018CBG, R7S910118CBG, R7S910027CBG, R7S910127CBG, R7S910028CBG, and R7S910128CBG only.

Note 2. For R7S910001CFP, R7S910101CFP, R7S910002CBG, R7S910102CBG, R7S910006CBG, R7S910106CBG,

R7S910011CBG, R7S910111CBG, R7S910015CBG, R7S910115CBG, R7S910016CBG, R7S910116CBG, R7S910025CBG,

R7S910125CBG, R7S910026CBG, and R7S910126CBG only.

Note 3. For R7S910035CBG, R7S910135CBG, R7S910036CBG, and R7S910136CBG only.

Table 2.10

Operating Frequency

Item

Symbol

min

max

Unit

Operating

frequency

CPU clock (CPUCLK)

150

600

MHz

150

450

150

300

System clock (ICLK)

150

Peripheral module clock (PCLKA)

150

Peripheral module clock (PCLKB)

Peripheral module clock (PCLKC)

150

Peripheral module clock (PCLKD)

Peripheral module clock (PCLKE)

18.75

Peripheral module clock (PCLKF)

7.5

Peripheral module clock (PCLKG)

7.5

Peripheral module clock (PCLKH)

High-speed serial clock (SERICLK)

120

150

ΔΣ interface clock output (DSCLK0, DSCLK1)

6.25

External bus clock output (CKIO)

18.75

External clock output for Ethernet PHY (CLKOUT25M)

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