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RZ/G2LC датащи(PDF) 62 Page - Renesas Technology Corp

номер детали RZ/G2LC
подробное описание детали  RZ 32 & 64-bit MPUs, RZ/G Series
PDF  74 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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RZ/G2LC датащи(HTML) 62 Page - Renesas Technology Corp

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RZ/G2L Group, RZ/G2LC Group
3. Electrical Characteristics
R01DS0484EJ0110
Rev.1.10
Page 62 of 74
May 30, 2025
3.5.19
Serial Communications Interface (SCIg) Access Timing
Table 3.46
SCIg Timing
Item
Symbol
Min.
Max.
Unit
Figures
SCIg
Input clock cycle
Asynchronous
tScyc
4
—
tp1cyc*
1
Figure 3.48
Clocked
synchronous
6
—
Input clock pulse width
tSCKW
0.4
0.6
tp1cyc*
1
Input clock rise time
tSCKr
—
5
ns
Input clock fall time
tSCKf
—
5
ns
Output clock cycle
Asynchronous*2
tScyc
8
—
tp1cyc*
1
Clocked
synchronous
4
—
Output clock pulse width
tSCKW
0.4
0.6
tp1cyc*
1
Output clock rise time
tSCKr
—
5
ns
Output clock fall time
tSCKf
—
5
ns
Transmit data delay time
Clocked
synchronous
tTXD
—
28
ns
Figure 3.49
Receive data setup time
Clocked
synchronous
tRXS
15
—
ns
Receive data hold time
Clocked
synchronous
tRXH
5
—
ns
Note:
AC access timing condition: drive ability 12mA, output load 30pF, slew rate = fast
Note 1.
tp1cyc indicates peripheral clock means SCIn_CLKP (P0
ϕ) (n = 0 to 1).
Note 2.
When the SEMR.ABCS0 and SEMR.BGDM bits are set to 1.
SCIn_SCK
(n = 0, 1)
tSCKW
tScyc
tSCKr
tSCKf
Figure 3.48
SCK Input Clock Timing



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