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ISO6042LDFPR датащи(PDF) 39 Page - Texas Instruments |
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ISO6042LDFPR датащи(HTML) 39 Page - Texas Instruments |
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39 / 52 page ![]() www.ti.com PACKAGE OUTLINE C 10.63 9.97 TYP 2.55 MAX 14X 1.27 16X 0.456 0.356 2X 8.89 (0.152) TYP 1 - 5 0.25 0.15 (1.4) 0.25 GAGE PLANE 0.962 0.708 A 10.5 10.1 NOTE 3 B 7.6 7.4 NOTE 4 4231632/A 02/2025 SOIC - 2.55 mm max height DW0016C-C01 SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. 1 16 0.25 C A B 9 8 PIN 1 ID AREA SEATING PLANE 0.1 C SEE DETAIL A TYPICAL DETAIL A SCALE 1.500 www.ti.com ISO6041 SLLSFV3A – DECEMBER 2025 – REVISED MARCH 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: ISO6041 |
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