1/9

September 2001

s

HIGH SPEED :

s

LOW POWER DISSIPATION:

s

COMPATIBLE WITH TTL OUTPUTS :

s

BALANCED PROPAGATION DELAYS:

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 75

DESCRIPTION

The M74HCT75 is an high speed CMOS 4 BIT D

technology.

It contains two groups of 2 bit latches controlled by

an enable input (G1

groups can be used in different circuits. Each latch

has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The

data applied to the data input is transferred to the

Q and Q outputs when the enable input is taken

high and the outputs will follow the data input as

long as the enable input is kept high. When the

enable input is taken low, the information data

applied to the data input is retained at the outputs.

The M74HCT75 is designed to directly interface

systems

with

TTL

and

NMOS

components.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M74HCT75

4 BIT D TYPE LATCH

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES

PACKAGE

TUBE

T & R

DIP

M74HCT75B1R

SOP

M74HCT75M1R

M74HCT75RM13TR

TSSOP

M74HCT75TTR

TSSOP

DIP

SOP