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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AS7341L датащи(PDF) 36 Page - ams-OSRAM AG |
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AS7341L датащи(HTML) 36 Page - ams-OSRAM AG |
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36 / 65 page  Document Feedback AS7341L Register Description Datasheet • PUBLIC DS000718 • v1-00 • 2020-May-25 64 │ 35 EDGE Register (Address 0x72) Figure 45: EDGE Register Addr: 0x72 EDGE Bit Bit Name Default Access Bit Description 7:0 SYNC_EDGE 0 RW Number of falling SYNC-edges between start and stop of integration in mode SYND Number of edges = SYNC_EDGE + 1 10.2.3 ADC Configuration (gain, AGC…) The following registers provide configuration for the 6 integrated ADCs (CH0 to CH5). It is possible to adjust the gain, configure and enable the automatic gain control (AGC) and setup the auto zero compensation for the engines. CFG1 Register (Address 0xAA) Figure 46: CFG1 Register Addr: 0xAA CFG1 Bit Bit Name Default Access Bit Description 7:5 reserved 0 reserved 4:0 AGAIN 9 RW Spectral Engines Gain Setting. Sets the spectral sensitivity. VALUE GAIN 0 0.5x 1 1x 2 2x 3 4x 4 8x 5 16x 6 32x 7 64x 8 128x 9 256x 10 512x |
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