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AS7341 датащи(PDF) 38 Page - ams-OSRAM AG |
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AS7341 датащи(HTML) 38 Page - ams-OSRAM AG |
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38 / 69 page ![]() Document Feedback AS7341 Register Description Datasheet • PUBLIC DS000504 • v3-00 • 2020-Jun-25 68 │ 37 10.2.3 ADC Configuration (gai n, AGC…) The following registers provide configuration for the 6 integrated ADCs (CH0 to CH5). It is possible to adjust the gain, configure and enable the automatic gain control (AGC) and setup the auto zero compensation for the engines. CFG1 Register (Address 0xAA) Figure 49: CFG1 Register Addr: 0xAA CFG1 Bit Bit Name Default Access Bit Description 7:5 reserved 0 reserved 4:0 AGAIN 9 RW Spectral engines gain setting. Sets the spectral sensitivity. VALUE GAIN 0 0.5x 1 1x 2 2x 3 4x 4 8x 5 16x 6 32x 7 64x 8 128x 9 256x 10 512x CFG10 Register (Address 0xB3) Figure 50: CFG10 Register Addr: 0xB3 CFG10 Bit Bit Name Default Access Bit Description 7:6 AGC_H 3 RW AGC High Hysteresis. Sets the data threshold at which AGAIN is reduced when spectral AGC mode is enabled. The threshold is automatically calculated internally as a percentage of full-scale. Note that full-scale is equal to (ATIME + 1) x (ASTEP + 1). |
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