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AS1710/AS1712

Datasheet - Application In form atio n

8.6 Driving Capacitive Loads

The AS1710/AS1712 amplifiers have a high tolerance for capacitive loads, and are stable with capacitive loads up to 100pF.

Figure 26 shows a typical non-inverting capacitive-load driving circuit in the unity-gain configuration.

Figure 26. Capacitive-Load Driving Circuit

Note:

Resistor RISO improves the circuit’s phase margin by isolating the load capacitor from the AS1710/AS1712 output.

8.7 Power-Up

The AS1710/AS1712 typically settle within 5µs after power-up.

8.8 Shutdown

When SHDNN (not included in B versions) is pulled low, supply current drops to 0.5µA (per amplifier, VDD = 2.7V), the amplifiers are disabled,

and their outputs are driven to VSS. Because the outputs are actively driven to VSS in shutdown, any pull-up resistor on the output causes a

current drain from the supply.

Note:

Pulling SHDNN high enables the amplifier. In the AS1712 the amplifiers shutdown in pairs.

When exiting shutdown, there is a 6µs delay before the amplifier output becomes active.

8.9 Power Supplies and Layout

The AS1710/AS1712 can operate from a single 2.7 to 5.5V supply or from dual ±1.35 to ±2.5V supplies. Good design improves device

performance by decreasing the amount of stray capacitance at the op-amp inputs/outputs.



For single-supply operation, bypass the power supply with a 0.1µF ceramic capacitor.



For dual-supply operation, bypass each supply to ground.



Decrease stray capacitance by placing external components close to the op-amp pins, minimizing trace and lead lengths.

RISO

–

+

AS1710

CF