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Revision 1.21

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AS1109

Datasheet - Detailed Descr i p ti on

The 8-bit data register will latch the data of the shift register at each rising edge of LD. This data is then used to drive the current generator output

drivers to switch on the corresponding LEDs as OEN goes low.

8.2 Timing Diagrams

This section contains timing diagrams referenced in other sections of this data sheet.

Figure 10. Normal Mode Timing Diagram

Figure 11. Output Delay Timing Diagram

OEN

OUTNx

LD

SDO

SDI

CLK

tSU(L)

tH(L)

tW(L)

tW(CLK)

tP1

tH(D)

50%

50%

50%

50%

50%

50%

tSU(D)

OEN Low = Output Enabled

tP2

OUTNx High = Output Off

OUTNx Low = Output On

50%

50%

50%

tW(OE)

7XtSTAG

tP3

OEN

OUTN0

OUTN1

OUTN7

50%

50%

50%

50%

tOF

tOR

tSTAG

90%

90%

10%

10%

7XtSTAG

tSTAG

tP3

50%

50%

50%

50%