RA4L1 datasheet(81/125 Pages) RENESAS

номер детали	RA4L1

подробное описание детали	Renesas Microcontrollers

PDF	125 Pages

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SDA

Timing

parameters

used

0.3 × VCC

0.7 × VCC

= Active Drive by Master

NM_SDA

CM_SDA

NM_SCL

CM_SCL

SCL

tSU_STO

tMMlock

tMMoverlap

tCAS

tSCO

0.3 × VCC

0.7 × VCC

0.3 × VCC

0.7 × VCC

0.3 × VCC

0.7 × VCC

0.3 × VCC

0.7 × VCC

0.3 × VCC

0.7 × VCC

OD or PP

Open-

Drain

OD or PP

Open-

Drain

= Open-Drain class Pull-Up by master

= High-Z by Master

Figure 2.51

I3C timing (open drain timing parameters)

2.3.13

SSIE Timing

Table 2.48

SSIE timing (1 of 2)

(1) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface, the

AC portion of the electrical characteristics is measured for each group.

Parameter

Symbol

Target

specification

Unit

Test

conditions

Min

Max

SSIBCK0

Cycle

Master

2.7v ≤ VCC ≤ 3.6

150

—

Figure 2.52

2.4 ≤ VCC < 2.7

200

—

1.8 ≤ VCC < 2.4

250

—

1.6 ≤ VCC < 1.8

1000

—

Slave

2.7v ≤ VCC ≤ 3.6

150

—

2.4 ≤ VCC < 2.7

200

—

1.8 ≤ VCC < 2.4

250

—

1.6 ≤ VCC < 1.8

1000

—

High level/ Low level

Master

tHC/tLC

0.35

—

Slave

0.35

—

Rising time/ falling

time

Master

tRC/tFC

—

0.15

tO / tI

Slave

—

0.15

tO / tI

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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