RA4E2 datasheet(54/91 Pages) RENESAS

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Table 2.30

IIC timing(1)-3

Setting of the SDA0_D, SCL0_D pins is not required with the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

IIC

(Fast-mode+)

BFCTL.FMPE = 1

SCL input cycle time

tSCL

10(18) × tI3Ccyc + 240

—

SCL input high pulse width

tSCLH

5(9) × tI3Ccyc + 120

—

SCL input low pulse width

tSCLL

5(9) × tI3Ccyc + 120

—

SCL, SDA rise time

tSr

—

120

SCL, SDA fall time

tSf

20 × (external pullup voltage/5.5

120

SCL, SDA input spike pulse removal

time

tSP

1(4) × tI3Ccyc

SDA input bus free time when

wakeup function is disabled

tBUF

5(9) × tI3Ccyc + 120

—

SDA input bus free time when

wakeup function is enabled

tBUF

5(9) × tI3Ccyc + 4 × tTcyc + 120

—

START condition input hold time

when wakeup function is disabled

tSTAH

tI3Ccyc + 120

—

START condition input hold time

when wakeup function is enabled

tSTAH

1(5) × tI3Ccyc + tTcyc + 120

—

Restart condition input setup time

tSTAS

120

—

Stop condition input setup time

tSTOS

120

—

Data input setup time

tSDAS

tI3Ccyc + 30

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*1

—

550

Note:

tI3Ccyc: I3C internal reference clock (I3Cφ) cycle, tTcyc: I3CCLK cycle.

Note:

Values in parentheses apply when INCTL.DNFS[3:0] is set to 0x3 while the digital filter is enabled with INCTL.DNFE set to 1.

Note 1. Cb indicates the total capacity of the bus line.

SDAn

SCLn

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

S*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Sr*1

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.41

I2C bus interface input/output timing

RA4E2 Datasheet

2. Electrical Characteristics

R01DS0413EJ0150 Rev.1.50

May 29, 2026

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