TMS320DM642 datasheet(63/176 Pages) TI

63 / 176 page

www.ti.com

3.5 Multiplexed Pin Configurations

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed.

Some of these pins are configured by software, and the others are configured by external pullup/pulldown

resistors only at reset. Those muxed pins that are configured by software should not be programmed to

switch functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown

resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after

reset. Table 3-8 identifies the multiplexed pins on the DM642 device; shows the default (primary) function

and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific

multiplexed functions.

Table 3-8. DM642 Device Multiplexed Pin Configurations(1)

MULTIPLEXED PINS

DEFAULT

DESCRIPTION

FUNCTION

SETTING

NAME

NO.

CLKOUT4/GP0[1]

CLKOUT4

GP1EN = 0 (disabled)

These pins are software-configurable. To use these pins

as GPIO pins, the GPxEN bits in the GPIO Enable

CLKOUT6/GP0[2]

CLKOUT6

GP2EN = 0 (disabled)

GPxEN = 1: GPx pin enabled

GPxDIR = 0: GPx pin is an input

GPxDIR = 1: GPx pin is an output

The VDAC output pin function is default.

To use GP0[8] as a GPIO pin, the PCI needs to be

disabled (PCI_EN = 0), the GPxEN bits in the GPIO

Enable Register and the GPxDIR bits in the GPIO

Direction Register must be properly configured.

GP8EN = 0 (disabled)

VDAC/GP0[8]

AD1

VDAC

MAC_EN = 0 (disabled)

GP8EN = 1: GP8 pin enabled

GP8DIR = 0: GP8 pin is an input

GP8DIR = 1: GP8 pin is an output

Note: If the PCI peripheral is disabled (PCI_EN pin = 0),

this pin must not be pulled up.

GP0[9]/PIDSEL

To use GP0[15:9] as GPIO pins, the PCI needs to be

GP0[10]/PCBE3

disabled (PCI_EN = 0), the GPxEN bits in the GPIO

GP0[11]/PREQ

Enable Register and the GPxDIR bits in the GPIO

GPxEN = 0 (disabled)

Direction Register must be properly configured.

GP0[12]/PGNT

None

PCI_EN = 0 (disabled)(1)

GPxEN = 1: GPx pin enabled

GP0[13]/PINTA

GPxDIR = 0: GPx pin is an input

GP0[14]/PCLK

GPxDIR = 1: GPx pin is an output

GP0[15]/PRST

VP1D[19]/AXR0[7]

AB12

VP1D[18]/AXR0[6]

AB11

By default, no function is enabled upon reset.

VP1D[17]/AXR0[5]

AC11

To enable the Video Port 1 data pins, the VP1EN bit in the

VP1EN bit = 0 (disabled) PERCFG register must be set to a 1. (McASP0 data pins

VP1D[16]/AXR0[4]

AD11

None

MCASP0EN bit = 0

are disabled).

VP1D[15]/AXR0[3]

AE11

(disabled)

To enable the McASP0[7:0] data pins, the MCASP0EN bit

VP1D[14]/AXR0[2]

AC10

in the PERCFG register must be set to a 1. (VP1 upper

VP1D[13]/AXR0[1]

AD10

data pins are disabled).

VP1D[12]/AXR0[0]

AC9

(1)

All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0].

Submit Documentation Feedback

Device Configurations

TMS320DM642 датащи(PDF) 63 Page - Texas Instruments

TMS320DM642 датащи(HTML) 63 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL