4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs

Datasheet

SMSC USB2226

11

Revision 1.4 (10-08-07)

DATASHEET

CF_D[7:0]

39

38

37

36

35

34

33

32

I/O8PD

CF Data 7-0:

The bi-directional data signals CF_D7-CF_D0 in the True IDE mode

data transfer.

In the True IDE Mode, all of task file register operation occur on the

CF_D[7:0], while the data transfer is on CF_D[15:0].

The bi-directional data signal has an internal weak pull-down resistor.

CF_IORDY

56

IPU

IO Ready:

This pin is active high input signal.

This pin has an internally controlled weak pull-up resistor.

CF_nCD2

54

IPU

CF Card Detection2:

This card detection pin is connected to the ground on the CF device,

when the CF device is inserted.

This pin has an internally controlled weak pull-up resistor.

CF_nCD1

53

IPU

CF Card Detection1:

This card detection pin is connected to ground on the CF device,

when the CF device is inserted.

This pin has an internally controlled weak pull-up resistor.

CF_nRESET

59

O8

CF Hardware Reset:

This pin is an active low hardware reset signal to CF device.

CF_nIOR

57

O8

CF IO Read:

This pin is an active low read strobe signal for CF device.

CF_nIOW

58

O8

CF IO Write Strobe:

This pin is an active low write strobe signal for CF device.

SmartMedia INTERFACE

SM_nWP

74

O8PD

SM Write Protect:

This pin is an active low write protect signal for the SM device.

This pin has a weak pull-down resistor that is permanently enabled.

SM_ALE

73

O8PD

SM Address Strobe:

This pin is an active high Address Latch Enable signal for the SM

device.

This pin has a weak pull-down resistor that is permanently enabled.

SM_CLE

75

O8PD

SM Command Strobe:

This pin is an active high Command Latch Enable signal for the SM

device.

This pin has a weak pull-down resistor that is permanently enabled.

SYMBOL

128-PIN

VTQFP

BUFFER

TYPE

DESCRIPTION