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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM647 датащи(PDF) 173 Page - Texas Instruments |
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TMS320DM647 датащи(HTML) 173 Page - Texas Instruments |
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173 / 182 page  VCLK VTXD[3:0] VRXD[3:0] 1 2 3 4 Data Data TMS320DM647/TMS320DM648 Digital Media Processor www.ti.com SPRS372B – MAY 2007 – REVISED APRIL 2008 Table 6-92. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the VLYNQ Module (see Figure 6-55) -720 -900 NO. PARAMETER UNIT MIN MAX 1 td(VCLKH-TXDI) Delay time, VCLK high to VTXD[3:0] invalid [SLOW Mode] 2.25 ns 1 td(VCLKH-TXDI) Delay time, VCLK high to VTXD[3:0] invalid [FAST Mode] 0.86 ns 2 td(VCLKH-TXDV) Delay time, VCLK to VTXD[3:0] valid 6.85 ns Table 6-93. Timing Requirements for Receive Data for the VLYNQ Module (see Figure 6-55) -720 -900 NO. UNIT MIN MAX RTM disabled 0.2 ns RTM enabled, RXD Flop = 0 1.25 ns RTM enabled, RXD Flop = 1 0.91 ns RTM enabled, RXD Flop = 2 0.64 ns Setup time, VRXD[3:0] valid before VCLK 3 tsu(RXDV-VCLKH) RTM enabled, RXD Flop = 3 0.36 ns high RTM enabled, RXD Flop = 4 0.09 ns RTM enabled, RXD Flop = 5 -0.18 ns RTM enabled, RXD Flop = 6 -0.44 ns RTM enabled, RXD Flop = 7 -0.69 ns RTM disabled 2 ns RTM enabled, RXD Flop = 0 0.95 ns RTM enabled, RXD Flop = 1 1.33 ns RTM enabled, RXD Flop = 2 1.72 ns 4 th(VCLKH-RXDV) Hold time, VRXD[3:0] valid after VCLK high RTM enabled, RXD Flop = 3 2.15 ns RTM enabled, RXD Flop = 4 2.58 ns RTM enabled, RXD Flop = 5 3.03 ns RTM enabled, RXD Flop = 6 3.46 ns RTM enabled, RXD Flop = 7 3.89 ns Figure 6-55. VLYNQ Transmit/Receive Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 173 |
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