TMS320DM647 datasheet(40/182 Pages) TI

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3.2.2

DSPBOOTADDR Register Description

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372B – MAY 2007 – REVISED APRIL 2008

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Table 3-3. DM648 Boot Modes

DEVICE BOOT AND

DM647/DM648

DSPBOOTADDR

CONFIGURATION PINS

BOOT DESCRIPTION(1)(2)

(Master/Slave)

(DEFAULT)

BOOTMODE[3:0]

UHPIEN

FASTBOOT

0000

0 or 1

No boot (emulation boot)

–

0x0080 0000

PCI boot no auto-initialization

Slave

0x0080 0000

0001

0 or 1

HPI boot

Slave

0x0080 0000

PCI boot with auto-initialization

Slave

0x0080 0000

0010

0 or 1

HPI boot

Slave

0x0080 0000

0011

0 or 1

UART boot with no hardware flow control

Slave

0x0080 0000

EMIFA ROM direct boot (PLL bypass mode)

Master

0xA000 0000

0100

0 or 1

EMIFA ROM AIS boot

Master

0x0080 0000

0101

0 or 1

I2C Boot (standard mode)

Master

0x0080 0000

0110

0 or 1

SPI boot

Master

0x0080 0000

0111

0 or 1

Reserved

–

0x0080 0000

1000

0 or 1

SGMII0 - Boot port, no packet forwarding

Slave

0x0080 0000

SGMII0 - Boot port, SGMII1 packet

1001

0 or 1

Slave

0x0080 0000

forwarding (reserved in DM647)

SGMII1 - Boot port, SGMII0 packet

1010

0 or 1

Slave

0x0080 0000

forwarding (reserved in DM647)

1011

0 or 1

Reserved

–

0x0080 0000

1100

0 or 1

Reserved

–

0x0080 0000

1101

0 or 1

Reserved

–

0x0080 0000

UART Boot with hardware flow control

1110

0 or 1

Slave

0x0080 0000

[UART0]

1111

0 or 1

Reserved

–

0x0080 0000

(1)

In all bootmodes other than EMIFA ROM Direct Boot (BOOTMODE[3:0] = 0100b, UHPIEN = 0b or 1b, FASTBOOT = 0b) all C64x+

cache is disabled (L1P,L1D,L2).

(2)

For details of the boot process, see Using the TMS320DM647 Bootloader Application Note (literature number SPRAAJ1).

The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register

format is shown in Figure 3-2 and bit field descriptions are shown in Table 3-4. DSPBOOTADDR is

readable and writable by software after reset. DSPBOOTADDR Decode: This decode logic determines the

default of the DSPBOOTADDR Register. It can default to the base address of L2 ROM (0x00800000) or

the base address of EMIFA CS2 (0xA0000000).

Figure 3-2. DSPBOOTADDR Register

BOOTADDR

Reserved

R/W-0100 0010 0010 0000 0000 00

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-4. DSPBOOTADDR Register Field Descriptions

Bit

Field

Value

Description

31:10

BOOTADDR

Upper 22 bits of the C64x+ DSP bootmode address

9:0

Reserved

Device Configuration

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