TMS320DM647 datasheet(167/182 Pages) TI

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6.20 Management Data Input/Output (MDIO)

6.20.1 MII Management Interface

6.20.2 MDIO Register Descriptions

TMS320DM647/TMS320DM648

Digital Media Processor

www.ti.com

SPRS372B – MAY 2007 – REVISED APRIL 2008

Table 6-81. Ethernet Subsystem Timing Requirements (continued)

PARAMETER(1)

MIN

NOM

MAX

UNITS

t03

REFCLKP/N rise/fall

700

t04

PLL Clock Period, x n Mode

t01 / n

t05

PLL power up

1 + 200 * C

µs

REFCLKP/N Jitter and PLL Loop Bandwidth

Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby

impairing system performance. A good quality, low jitter reference clock is necessary to achieve

compliance with most if not all physical layer standards (see Table 6-82).

Table 6-82. REFCLKP/N Jitter Requirements for Standards Compliance

Standard

Line Rate (Gbps)

Total REFCLKP/N Jitter (within PLL bandwidth)

Gigabit Ethernet

1.25

50 ps pk-pk

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to

enumerate all PHY devices in the system. It contains two user access registers to control and monitor up

to two PHYs simultaneously.

The MDIO module implements the 802.3 serial management interface to interrogate and control two

Ethernet PHYs simultaneously using a shared two-wire bus.

Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached

to the Ethernet Switch Subsystem, retrieve the negotiation results, and configure required parameters in

the Ethernet Switch Subsystem module for correct operation. The module is designed to allow almost

transparent operation of the MDIO interface, with very little maintenance from the core processor. Only a

maximum of two PHYs may be connected at any given time.

For more detailed information on the Ethernet Switch Subsystem, see the TMS320DM647/DM648 DSP

Ethernet Subsystem User's Guide Reference Guide (literature number SPRUF57).For a list of supported

registers and register fields, see Table 6-83.

Table 6-83. MDIO Registers

HEX ADDRESS RANGE

DESCRIPTION

0x02D0 4000

MDIOVER

Module version register

0x02D0 4004

MDIOCONTROL

Module control register

0x02D0 4008

MDIOALIVE

PHY acknowledge status register

0x02D0 400C

MDIOLINK

PHY link status register

0x02D0 4010

MDIOLINKINTRAW

Link status change interrupt register (raw

value)

0x02D0 4014

MDIOLINKINTMASKED

Link status change interrupt register (masked

value)

0x02D0 4018 - 0x02D0 401C

reserved

0x02D0 4020

MDIOUSERINTRAW

User command complete interrupt register

(raw value)

0x02D0 4024

MDIOUSERINTMASKED

User command complete interrupt register

(masked value)

0x02D0 4028

MDIOUSERINTMASKSET

User interrupt mask set register

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